The present invention relates generally to logic circuits of the type fabricated on a monolithic semiconductor chip employing insulated-gate field-effect transistors (IGFETs) and, more paricularly, to a Reset/Set (R/S) latch.
As is known, an R/S latch is a form of flip-flop useful in digital logic applications. An R/S latch has a pair of inputs, designed Set (S) and Reset (R), and a pair of normally-complementary data outputs, Q and Q.
Operation of a NOR R/S latch is defined in accordance with the following truth table, where "L" denotes a logic "low" level, also known as binary "0", and "H" denotes a logic "high" level, also known as binary "1". The notation "N/C" means "no change", indicating that the latch outputs remain unchanged for the particular combination of inputs indicated:
______________________________________ R/S LATCH TRUTH TABLE Inputs Outputs R S Q Q ______________________________________ L L N/C N/C L H H L H L L H H H L L ______________________________________
As is known, large scale integrated circuits typically comprise a multiplicity of individual logic elements formed on a single integrated circuit employing, for example, metal-oxide-semiconductor (MOS) technology or a form thereof. In the design of such circuits, important considerations are minimizing the transistor count thereby reducing the circuit area required for each individual logic element and maintaining low power dissipation.